4
Functional Description ...............................................................................................4-1
4.1
System Address Map....................................................................................4-1
4.1.1 Memory Address Ranges ................................................................4-2
4.1.1.1 Compatibility Area...............................................................4-3
4.1.1.2 Extended Memory Area ......................................................4-4
4.1.1.3 AGP Memory Address Range.............................................4-6
4.1.1.4 AGP DRAM Graphics Aperture...........................................4-6
4.1.1.5 System Management Mode (SMM) Memory Range...........4-6
4.1.2 Memory Shadowing .........................................................................4-8
4.1.3 I/O Address Space...........................................................................4-8
4.1.4 AGP I/O Address Mapping...............................................................4-8
4.1.5 Decode Rules and Cross-Bridge Address Mapping ........................4-9
4.1.5.1 PCI Interface Decode Rules ...............................................4-9
4.1.5.2 AGP Interface Decode Rules..............................................4-9
4.1.5.3 Legacy VGA Ranges ........................................................4-10
Host Interface..............................................................................................4-10
4.2.1 Host Bus Device Support...............................................................4-10
4.2.2 Symmetric Multiprocessor (SMP) Protocol Support.......................4-13
4.2.3 In-Order Queue Pipelining .............................................................4-13
4.2.4 Frame Buffer Memory Support (USWC)........................................4-13
DRAM Interface ..........................................................................................4-14
4.3.1 DRAM Organization and Configuration..........................................4-14
4.3.1.1 Configuration Mechanism For DIMMS..............................4-19
4.3.2 DRAM Address Translation and Decoding ....................................4-20
4.3.3 SDRAMC Register Programming ..................................................4-23
4.3.4 DRAMT Register Programming .....................................................4-23
4.3.5 SDRAM Paging Policy ...................................................................4-24
PCI Interface...............................................................................................4-24
AGP Interface .............................................................................................4-24
Data Integrity Support.................................................................................4-25
4.6.1 Data Integrity Mode Selection........................................................4-25
4.6.1.1 Non-ECC (Default Mode of Operation).............................4-25
4.6.1.2 EC Mode...........................................................................4-25
4.6.1.3 ECC Mode ........................................................................4-25
4.6.1.4 ECC Generation and Error Detection/Correction
4.2
4.3
4.4
4.5
4.6
and Reporting ...................................................................4-26
4.6.1.5 Optimum ECC Coverage ..................................................4-27
4.6.2 DRAM ECC Error Signaling Mechanism........................................4-27
4.6.3 CPU Bus Integrity ..........................................................................4-27
4.6.4 PCI Bus Integrity............................................................................4-27
System Clocking .........................................................................................4-28
Power Management....................................................................................4-28
4.8.1 Overview........................................................................................4-28
4.8.2 82443BX Reset..............................................................................4-32
4.8.2.1 CPU Reset........................................................................4-33
4.8.2.2 CPU Clock Ratio Straps....................................................4-33
4.8.2.3 82443BX Straps................................................................4-34
4.8.3 Suspend Resume ..........................................................................4-34
4.8.3.1 Suspend Resume protocols..............................................4-34
4.8.3.2 Suspend Refresh ..............................................................4-34
4.8.4 Clock Control Functions.................................................................4-35
4.8.5 SDRAM Power Down Mode...........................................................4-36
4.7
4.8
82443BX Host Bridge Datasheet
vii
ETC [ ETC ]
