R
XC5200 Series Field Programmable Gate Arrays
Pin
Description
VQ64*
PC84
PQ100
VQ100
TQ144
PG156
Boundary Scan Order
CCLK
48
-
73
74
75
76
77
78
79
80
-
77
78
79
80
81
82
83
84
-
74
75
76
77
78
79
80
81
-
107
108
109
110
111
112
115
116
118
121
122
123
124
125
126
127
R2
P3
T1
N3
R1
P2
P1
N1
L3
K3
K2
K1
J1
-
VCC
-
74.
I/O (TDO)
GND
49
-
0
-
75.
76.
77.
78.
I/O (A0, WS)
GCK4 (A1, I/O)
I/O (A2, CS1)
I/O (A3)
GND
50
51
52
-
9
15
18
21
-
-
79.
80.
81.
82.
83.
84.
I/O (A4)
I/O (A5)
I/O
-
81
82
-
85
86
87
88
89
90
91
82
83
84
85
86
87
88
27
30
33
39
42
45
-
53
-
I/O
-
-
I/O (A6)
I/O (A7)
GND
54
55
56
83
84
1
J2
J3
H2
* VQ64 package supports Master Serial, Slave Serial, and Express configuration modes only.
Additional No Connect (N.C.) Connections on TQ144 Package
TQ144
135
136
140
141
4
9
41
42
46
47
62
63
67
68
77
78
82
83
98
117
10
25
26
30
31
99
119
120
103
104
113
114
7
5
Notes: Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD
Pin Locations for XC5204 Devices
The following table may contain pinout information for unsupported device/package combinations. Please see the
availability charts elsewhere in the XC5200 Series data sheet for availability information.
Pin
Description
VCC
PC84
PQ100 VQ100
TQ144
128
129
130
131
132
133
134
135
136
137
-
PG156 PQ160
Boundary Scan Order
2
3
4
-
92
93
94
95
96
97
98
-
89
90
91
92
93
94
95
-
H3
H1
G1
G2
G3
F1
F2
E1
E2
F3
D1
D2
E3
C1
C2
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
-
1.
2.
3.
4.
5.
6.
7.
8.
I/O (A8)
I/O (A9)
I/O
78
81
87
I/O
-
90
I/O (A10)
I/O (A11)
I/O
5
6
-
93
99
102
105
-
I/O
-
-
-
GND
-
-
-
9.
I/O
-
-
-
111
114
117
123
126
10.
11.
12.
13.
I/O
-
-
-
-
I/O (A12)
I/O (A13)
I/O
7
8
-
99
100
-
96
97
-
138
139
140
November 5, 1998 (Version 5.2)
7-135
ETC [ ETC ]
