R
XC5200 Series Field Programmable Gate Arrays
non-zero hold, attach a NODELAY attribute or property to
the flip-flop or input buffer.
For XC5200 devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
pin pair. For some XC5200 devices, additional internal
Power/Ground pin pairs are connected to special Power
and Ground planes within the packages, to reduce ground
bounce.
IOB Output Signals
Output signals can be optionally inverted within the IOB,
and pass directly to the pad. As with the inputs, a CLB
flip-flop or latch can be used to store the output signal.
For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC5200 devices. This maxi-
mum capacitive load should not be exceeded, as it can
result in ground bounce of greater than 1.5 V amplitude and
more than 5 ns duration. This level of ground bounce may
cause undesired transient behavior on an output, or in the
internal logic. This restriction is common to all high-speed
digital ICs, and is not particular to Xilinx or the XC5200
Series.
An active-High 3-state signal can be used to place the out-
put buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control,
the output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these signals is independently
configured for each IOB.
The XC5200 devices provide a guaranteed output sink cur-
rent of 8 mA.
Supported destinations for XC5200-Series device outputs
are shown in Table 6.(For a detailed discussion of how to
interface between 5 V and 3.3 V devices, see the 3V Prod-
ucts section of The Programmable Logic Data Book.)
XC5200-Series devices have a feature called “Soft
Start-up,” designed to reduce ground bounce when all out-
puts are turned on simultaneously at the end of configura-
tion. When the configuration process is finished and the
device starts up, the first activation of the outputs is auto-
matically slew-rate limited. Immediately following the initial
activation of the I/O, the slew rate of the individual outputs
is determined by the individual configuration option for
each IOB.
An output can be configured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure 12.)
Table 6: Supported Destinations for XC5200-Series
Outputs
Global Three-State
XC5200 Output Mode
A separate Global 3-State line (not shown in Figure 11)
forces all FPGA outputs to the high-impedance state,
unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not com-
pete with other routing resources; it uses a dedicated distri-
bution network.
5 V,
CMOS
Destination
XC5200 device, V =3.3 V,
CC
√
some
√
CMOS-threshold inputs
Any typical device, V = 3.3 V,
1
CC
CMOS-threshold inputs
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin loca-
tion can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad. An
inverter can optionally be inserted after the input buffer to
invert the sense of the Global 3-State signal. Using GTS is
similar to Global Reset. See Figure 8 on page 90 for
details. Alternatively, GTS can be driven from any internal
node.
Any device, V = 5 V,
CC
TTL-threshold inputs
Any device, V = 5 V,
CC
√
CMOS-threshold inputs
1. Only if destination device has 5-V tolerant inputs
OPAD
Other IOB Options
OBUFT
X6702
There are a number of other programmable options in the
XC5200-Series IOB.
Figure 12: Open-Drain Output
Pull-up and Pull-down Resistors
Output Slew Rate
Programmable IOB pull-up and pull-down resistors are
useful for tying unused pins to Vcc or Ground to minimize
power consumption and reduce noise sensitivity. The con-
figurable pull-up resistor is a p-channel transistor that pulls
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-criti-
cal signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
7-92
November 5, 1998 (Version 5.2)
ETC [ ETC ]
