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XC5202-5VQ100I 参数 Datasheet PDF下载

XC5202-5VQ100I图片预览
型号: XC5202-5VQ100I
PDF下载: 下载PDF文件 查看货源
内容描述: 现场可编程门阵列(FPGA)的\n [Field Programmable Gate Array (FPGA) ]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 73 页 / 583 K
品牌: ETC [ ETC ]
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R
XC5200 Series Field Programmable Gate Arrays  
to Vcc. The configurable pull-down resistor is an n-channel  
transistor that pulls to Ground.  
The value of these resistors is 20 kΩ − 100 k. This high  
value makes them unsuitable as wired-AND pull-up resis-  
tors.  
OSC1  
OSCS  
OSC2  
The pull-up resistors for most user-programmable IOBs are  
active during the configuration process. See Table 13 on  
page 124 for a list of pins with pull-ups active before and  
during configuration.  
OSC1  
CK_DIV  
OSC2  
After configuration, voltage levels of unused pads, bonded  
or unbonded, must be valid logic levels, to reduce noise  
sensitivity and avoid excess current. Therefore, by default,  
unused pads are configured with the internal pull-up resis-  
tor active. Alternatively, they can be individually configured  
with the pull-down resistor, or as a driven output, or to be  
driven by an external source. To activate the internal  
pull-up, attach the PULLUP library component to the net  
attached to the pad. To activate the internal pull-down,  
attach the PULLDOWN library component to the net  
attached to the pad.  
5200_14  
Figure 13: XC5200 Oscillator Macros  
VersaBlock Routing  
The General Routing Matrix (GRM) connects to the  
Versa-Block via 24 bidirectional ports (M0-M23). Excluding  
direct connections, global nets, and 3-statable Longlines,  
all VersaBlock inputs and outputs connect to the GRM via  
these 24 ports. Four 3-statable unidirectional signals  
(TQ0-TQ3) drive out of the VersaBlock directly onto the  
horizontal and vertical Longlines. Two horizontal global  
nets and two vertical global nets connect directly to every  
CLB clock pin; they can connect to other CLB inputs via the  
GRM. Each CLB also has four unidirectional direct con-  
nects to each of its four neighboring CLBs. These direct  
connects can also feed directly back to the CLB (see  
Figure 14).  
JTAG Support  
Embedded logic attached to the IOBs contains test struc-  
tures compatible with IEEE Standard 1149.1 for boundary  
scan testing, simplifying board-level testing. More informa-  
tion is provided in “Boundary Scan” on page 98.  
7
Oscillator  
XC5200 devices include an internal oscillator. This oscilla-  
tor is used to clock the power-on time-out, clear configura-  
tion memory, and source CCLK in Master configuration  
modes. The oscillator runs at a nominal 12 MHz frequency  
that varies with process, Vcc, and temperature. The output  
CCLK frequency is selectable as 1 MHz (default), 6 MHz,  
or 12 MHz.  
In addition, each CLB has 16 direct inputs, four direct con-  
nections from each of the neighboring CLBs. These direct  
connections provide high-speed local routing that  
bypasses the GRM.  
Local Interconnect Matrix  
The Local Interconnect Matrix (LIM) is built from input and  
output multiplexers. The 13 CLB outputs (12 LC outputs  
The XC5200 oscillator divides the internal 12-MHz clock or  
a user clock. The user then has the choice of dividing by 4,  
16, 64, or 256 for the “OSC1” output and dividing by 2, 8,  
32, 128, 1024, 4096, 16384, or 65536 for the “OSC2” out-  
put. The division is specified via a “DIVIDEn_BY=x”  
attribute on the symbol, where n=1 for OSC1, or n=2 for  
OSC2. These frequencies can vary by as much as -50% or  
+ 50%.  
plus a V /GND signal) connect to the eight VersaBlock  
cc  
outputs via the output multiplexers, which consist of eight  
fully populated 13-to-1 multiplexers. Of the eight  
VersaBlock outputs, four signals drive each neighboring  
CLB directly, and provide a direct feedback path to the input  
multiplexers. The four remaining multiplexer outputs can  
drive the GRM through four TBUFs (TQ0-TQ3). All eight  
multiplexer outputs can connect to the GRM through the  
bidirectional M0-M23 signals. All eight signals also connect  
to the input multiplexers and are potential inputs to that  
CLB.  
The OSC5 macro is used where an internal oscillator is  
required. The CK_DIV macro is applicable when a user  
clock input is specified (see Figure 13).  
November 5, 1998 (Version 5.2)  
7-93