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NT5DS16M8AT-7K 参数 Datasheet PDF下载

NT5DS16M8AT-7K图片预览
型号: NT5DS16M8AT-7K
PDF下载: 下载PDF文件 查看货源
内容描述: DDR同步DRAM [DDR Synchronous DRAM ]
分类和应用: 内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 76 页 / 1242 K
品牌: ETC [ ETC ]
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NT5DS32M4AT  
NT5DS16M8AT  
128Mb Double Data Rate SDRAM  
Power-Down  
Power-down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are  
idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode  
is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK and CKE.  
The DLL is still running in Power Down mode, so for maximum power savings, the user has the option of disabling the DLL prior  
to entering Power-down. In that case, the DLL must be enabled after exiting power-down, and 200 clock cycles must occur  
before a Read command can be issued. In Power Down mode, CKE Low and a stable clock signal must be maintained at the  
inputs of the DDR SDRAM, and all other input signals are Don’ t Care. However, power-down duration is limited by the refresh  
requirements of the device, so in most applications, the self refresh mode is preferred over the DLL-disabled power-down  
mode.  
The power-down state is synchronously exited when CKE is registered high (along with a Nop or Deselect command). A valid,  
executable command may be applied one clock cycle later.  
Power Down  
CK  
CK  
t
t
IS  
IS  
CKE  
Command  
VALID  
NOP  
VALID  
NOP  
No column  
access in  
progress  
Exit  
power down  
mode  
Don’ t Care  
Enter Power Down mode  
(Burst Read or Write operation  
must not be in progress)  
44  
REV 1.0  
May, 2001  
©
NANYA TECHNOLOGY CORP. All rights reserved.  
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.  
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