Figure 13.38 Example of Buffer Operation (1)
(Buffer Operation for Output Compare Register)..................................................218
Figure 13.39 Example of Compare Match Timing for Buffer Operation ...................................219
Figure 13.40 Example of Buffer Operation (2)
(Buffer Operation for Input Capture Register).......................................................220
Figure 13.41 Input Capture Timing of Buffer Operation............................................................221
Figure 13.42 Buffer Operation (3)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............222
Figure 13.43 Buffer Operation (4)
(Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) ............223
Figure 13.44 Example of Output Disable Timing of Timer Z by Writing to TOER ..................224
Figure 13.45 Example of Output Disable Timing of Timer Z by External Trigger....................224
Figure 13.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR ...................225
Figure 13.47 Example of Output Inverse Timing of Timer Z by Writing to POCR...................225
Figure 13.48 IMF Flag Set Timing when Compare Match Occurs.............................................226
Figure 13.49 IMF Flag Set Timing at Input Capture ..................................................................227
Figure 13.50 OVF Flag Set Timing............................................................................................227
Figure 13.51 Status Flag Clearing Timing..................................................................................228
Figure 13.52 Contention between TCNT Write and Clear Operations.......................................228
Figure 13.53 Contention between TCNT Write and Increment Operations ...............................229
Figure 13.54 Contention between GR Write and Compare Match.............................................230
Figure 13.55 Contention between TCNT Write and Overflow...................................................231
Figure 13.56 Contention between GR Read and Input Capture..................................................232
Figure 13.57 Contention between Count Clearing and Increment Operations
by Input Capture ...................................................................................................232
Figure 13.58 Contention between GR Write and Input Capture.................................................233
Section 14 Watchdog Timer
Figure 14.1 Block Diagram of Watchdog Timer ........................................................................235
Figure 14.2 Watchdog Timer Operation Example......................................................................238
Section 15 14-Bit PWM
Figure 15.1 Block Diagram of 14-Bit PWM...............................................................................239
Figure 15.2 Waveform Output by 14-Bit PWM .........................................................................242
Section 16 Serial Communication Interface 3 (SCI3)
Figure 16.1 Block Diagram of SCI3...........................................................................................245
Figure 16.2 Data Format in Asynchronous Communication ......................................................260
Figure 16.3 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits)...............260
Figure 16.4 Sample SCI3 Initialization Flowchart .....................................................................261
Figure 16.5 Example of SCI3 Transmission in Asynchronous Mode
(8-Bit Data, Parity, One Stop Bit)............................................................................262
Figure 16.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)......................263
Rev. 3.00, 05/03, page xxii of xxx
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