23.3.8 Power-On Reset Circuit Characteristics (Optional).............................................402
23.4 Operation Timing..............................................................................................................403
23.5 Output Load Condition .....................................................................................................406
Appendix A Instruction Set...............................................................................407
A.1 Instruction List..................................................................................................................407
A.2 Operation Code Map.........................................................................................................422
A.3 Number of Execution States..............................................................................................425
A.4 Combinations of Instructions and Addressing Modes ......................................................436
Appendix B I/O Port Block Diagrams...............................................................437
B.1 I/O Port Block Diagrams...................................................................................................437
B.2 Port States in Each Operating State...................................................................................454
Appendix C Product Code Lineup.....................................................................455
Appendix D Package Dimensions.....................................................................457
Appendix E EEPROM Laminated-Structure Cross-Sectional View.................459
Main Revisions and Additions in this Edition.....................................................461
Index
.........................................................................................................469
Rev. 3.00, 05/03, page xviii of xxx
ETC [ ETC ]
