Section 18 A/D Converter
Figure 18.1 Block Diagram of A/D Converter ...........................................................................318
Figure 18.2 A/D Conversion Timing..........................................................................................324
Figure 18.3 External Trigger Input Timing ................................................................................325
Figure 18.4 A/D Conversion Accuracy Definitions (1)..............................................................326
Figure 18.5 A/D Conversion Accuracy Definitions (2)..............................................................327
Figure 18.6 Analog Input Circuit Example.................................................................................328
Section 19 EEPROM
Figure 19.1 Block Diagram of EEPROM...................................................................................330
Figure 19.2 EEPROM Bus Format and Bus Timing...................................................................332
Figure 19.3 Byte Write Operation ..............................................................................................335
Figure 19.4 Page Write Operation..............................................................................................335
Figure 19.5 Current Address Read Operation.............................................................................337
Figure 19.6 Random Address Read Operation ...........................................................................337
Figure 19.7 Sequential Read Operation (when current address read is used).............................338
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional)
Figure 20.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit....342
Figure 20.2 Operational Timing of Power-On Reset Circuit......................................................345
Figure 20.3 Operational Timing of LVDR Circuit .....................................................................346
Figure 20.4 Operational Timing of LVDI Circuit.......................................................................347
Figure 20.5 Timing for Operation/Release of Low-Voltage Detection Circuit ..........................348
Section 21 Power Supply Circuit
Figure 21.1 Power Supply Connection when Internal Step-Down Circuit is Used ....................349
Figure 21.2 Power Supply Connection when Internal Step-Down Circuit is Not Used .............350
Section 23 Electrical Characteristics
Figure 23.1 System Clock Input Timing.....................................................................................403
Figure 23.2 RES Low Width Timing..........................................................................................403
Figure 23.3 Input Timing............................................................................................................403
Figure 23.4 I2C Bus Interface Input/Output Timing ...................................................................404
Figure 23.5 SCK3 Input Clock Timing.......................................................................................404
Figure 23.6 SCI Input/Output Timing in Clocked Synchronous Mode ......................................405
Figure 23.7 EEPROM Bus Timing.............................................................................................405
Figure 23.8 Output Load Circuit.................................................................................................406
Appendix B I/O Port Block Diagrams
Figure B.1 Port 1 Block Diagram (P17) .....................................................................................437
Figure B.2 Port 1 Block Diagram (P14, P16) .............................................................................438
Figure B.3 Port 1 Block Diagram (P15) .....................................................................................439
Figure B.4 Port 1 Block Diagram (P12) .....................................................................................439
Figure B.5 Port 2 Block Diagram (P11) .....................................................................................440
Figure B.6 Port 1 Block Diagram (P10) .....................................................................................441
Figure B.7 Port 2 Block Diagram (P24, P23) .............................................................................441
Rev. 3.00, 05/03, page xxiv of xxx
ETC [ ETC ]
