16.3.5 Serial Mode Register (SMR)................................................................................248
16.3.6 Serial Control Register 3 (SCR3).........................................................................249
16.3.7 Serial Status Register (SSR).................................................................................251
16.3.8 Bit Rate Register (BRR) ......................................................................................253
16.4 Operation in Asynchronous Mode ....................................................................................260
16.4.1 Clock....................................................................................................................260
16.4.2 SCI3 Initialization................................................................................................261
16.4.3 Data Transmission................................................................................................262
16.4.4 Serial Data Reception...........................................................................................264
16.5 Operation in Clocked Synchronous Mode ........................................................................267
16.5.1 Clock....................................................................................................................267
16.5.2 SCI3 Initialization................................................................................................267
16.5.3 Serial Data Transmission .....................................................................................268
16.5.4 Serial Data Reception (Clocked Synchronous Mode)..........................................270
16.5.5 Simultaneous Serial Data Transmission and Reception.......................................272
16.6 Multiprocessor Communication Function.........................................................................274
16.6.1 Multiprocessor Serial Data Transmission ............................................................276
16.6.2 Multiprocessor Serial Data Reception..................................................................277
16.7 Interrupts...........................................................................................................................281
16.8 Usage Notes ......................................................................................................................282
16.8.1 Break Detection and Processing...........................................................................282
16.8.2 Mark State and Break Sending.............................................................................282
16.8.3 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).....................................................................282
16.8.4 Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode ............................................................................................283
Section 17 I2C Bus Interface 2 (IIC2)............................................................... 285
17.1 Features.............................................................................................................................285
17.2 Input/Output Pins ..............................................................................................................287
17.3 Register Descriptions ........................................................................................................287
17.3.1 I2C Bus Control Register 1 (ICCR1)....................................................................288
17.3.2 I2C Bus Control Register 2 (ICCR2)....................................................................290
17.3.3 I2C Bus Mode Register (ICMR)...........................................................................291
17.3.4 I2C Bus Interrupt Enable Register (ICIER)..........................................................293
17.3.5 I2C Bus Status Register (ICSR)............................................................................295
17.3.6 Slave Address Register (SAR).............................................................................297
17.3.7 I2C Bus Transmit Data Register (ICDRT) ...........................................................298
17.3.8 I2C Bus Receive Data Register (ICDRR).............................................................298
17.3.9 I2C Bus Shift Register (ICDRS)...........................................................................298
17.4 Operation...........................................................................................................................299
17.4.1 I2C Bus Format ....................................................................................................299
17.4.2 Master Transmit Operation ..................................................................................300
Rev. 3.00, 05/03, page xv of xxx
ETC [ ETC ]
