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CXD3018Q/R 参数 Datasheet PDF下载

CXD3018Q/R图片预览
型号: CXD3018Q/R
PDF下载: 下载PDF文件 查看货源
内容描述: CD数字信号处理器,内置DigitalServo和DAC [CD Digital Signal Processor with Built-in DigitalServo and DAC ]
分类和应用: 数字信号处理器
文件页数/大小: 134 页 / 942 K
品牌: ETC [ ETC ]
 浏览型号CXD3018Q/R的Datasheet PDF文件第40页浏览型号CXD3018Q/R的Datasheet PDF文件第41页浏览型号CXD3018Q/R的Datasheet PDF文件第42页浏览型号CXD3018Q/R的Datasheet PDF文件第43页浏览型号CXD3018Q/R的Datasheet PDF文件第45页浏览型号CXD3018Q/R的Datasheet PDF文件第46页浏览型号CXD3018Q/R的Datasheet PDF文件第47页浏览型号CXD3018Q/R的Datasheet PDF文件第48页  
CXD3018Q/R  
$AD commands (preset: $AD00)  
Data 1  
Data 2  
Data 3  
Data 4  
Command  
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0  
AD  
(Sleep setting)  
DSP DSSP ASYM  
SLEEP SLEEP SLEEP  
LPF  
SLEEP  
1
1
0
1
ADCPS  
0
0
0
ADCPS:  
This bit sets the operation mode of the DSSP block A/D converter.  
When 0, the operation mode of the DSSP block A/D converter is set to normal. (default)  
When 1, the operation mode of the DSSP block A/D converter is set to power saving.  
DSP SLEEP: This bit sets the operation mode of the DSP block.  
When 0, the DSP block operates normally. (default)  
When 1, the DSP block clock is stopped. This makes it possible to reduce power consumption.  
DSSP SLEEP: This bit sets the operation mode of the DSSP block.  
When 0, the DSSP block operates normally. (default)  
When 1, the DSSP block clock is stopped. In addition, the A/D converter and operational  
amplifier in the DSSP block are set to standby mode. This makes it possible to reduce power  
consumption.  
ASYM SLEEP: This bit sets the operation mode of the asymmetry correction circuit and VCO1.  
When 0, the asymmetry correction circuit and VCO1 operate normally. (default)  
When 1, the operational amplifier in the asymmetry correction circuit is set to standby mode. In  
addition, the multiplier PLL VCO1 oscillation is stopped. This makes it possible to reduce  
power consumption.  
LPF SLEEP: This bit sets the operation mode of the analog low-pass filter block.  
When 0, the analog low-pass filter block operates normally. (default)  
When 1, the analog low-pass filter block is set to standby mode. This makes it possible to  
reduce power consumption.  
The DAC block clock can be stopped by setting $9 command DACPWDN (when OPSL1 = 1).  
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