CXD3018Q/R
(2) CLOK, DATA, XLAT, COUT, SQCK, and EXCK pins
(VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Clock frequency
Clock pulse width
Setup time
Symbol
Min.
Typ.
Max.
0.65
Unit
MHz
ns
fCK
t
t
t
t
t
WCK
SU
H
750
300
300
300
750
ns
Hold time
ns
Delay time
D
ns
Latch pulse width
WL
ns
EXCK, SQCK frequency fT
EXCK, SQCK pulse width fWT
0.65Note) MHz
ns
750Note)
1/fCK
tWCK
tWCK
CLOK
DATA
XLAT
tSU
tH
tD
tWL
EXCK
SQCK
tWT
tWT
1/fT
SBSO
SQSO
tSU
tH
Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum
operating frequency is 300kHz and its minimum pulse width is 1.5µs.
(3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 3.3 ± 0.3V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Typ.
Max.
Unit
ns
Conditions
Min.
94
BCK pulse width
t
t
t
t
W
18
DATAL, R setup time
DATAL, R hold time
LRCK setup time
ns
SU
H
18
ns
18
ns
SU
tW(BCKI) tW(BCKI)
VDD/2
VDD/2
BCKI
tSU
tH
(PCMDI)
(PCMDI)
PCMDI
LRCKI
tSU
(LRCKI)
– 11 –
ETC [ ETC ]
