July 2004
AS91L1006BU
AS91L1006BU Detailed Mode of Operation
Addressing the AS91L1006BU device
The AS91L1006BU device should be in
the Wait-for-Selection mode, which can be
entered into by issuing an asynchronous reset
(through the deassertion of TRST) or by issuing a
synchronous reset (through the assertion of TMS
for five cycles of TCK). After the device has been
After a Test-Logic-Reset or power-up, the
AS91L1006BU device will be in its Wait-for-
Selection state with its TDO pin tri-stated, thus
avoiding contention in a Multi-Drop environment.
The AS91L1006BU device will respond to a
device-select sequence for a particular address
that is auto generated by third party test tools with
respect to the address that is pre-loaded on its
S(5..0). Once this sequence has been completed,
the AS91L1006BU device will respond to normal
IEEE 1149.1 instructions. Note that addresses 60-
63 have been reserved and the AS91L1006BU
device will not respond if the user selects these
addresses.
selected, it can be issued
instruction.
a
GOTOWAIT
The internal IEEE1149.1 state machine of
the AS91L1006BU device is taken to the Shift-IR
phase and the required Device-ID is shifted into
the Instruction register. As the IEEE1149.1 state
machine passes through the Update-IR phase,
the address is matched to the value on the S(5-0)
pins on the AS91L1006BU device; if the values
match, then the AS91L1006BU device is selected
and is ready to receive any normal IEEE1149.1
command.
S(5-0) value
IR (7 – 0) value
< 3A hex or 60
decimal
XXVVVVVV
Table 1 - AS91L1006BU
Device Selection Table
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3
ETC [ ETC ]
