Serial In pu t Form ats
Righ t Ch an n el
Left Ch an n el
WDCLK (Fs, 50% du ty cycle sh own )
DIN, 32 bits/ fram e
23
23
0
Don 't Care
23
0
Don 't Care
DIN, 24 bits/ fram e
0
23
0
Tim in g Exam ple
32 bits/ frame
WDCLK (Fs, 50% du ty cycle sh own )
64Fs bitclk (in ternal)
LEFT
RIGHT
DIN
VALID
100 n s10 0n s
VALID
10 0n s1 00n s
VALID
100n s 100n s
VALID
100n s 100n s
Ts/ 128
Ts/ 128
Ts/ 64
Ts/ 64
24 bits/ frame
LEFT
WDCLK (Fs, 50% du ty cycle sh own )
48Fs bitclk (in ternal)
RIGHT
DIN
VALID
100 n s10 0n s
VALID
10 0n s1 00n s
VALID
100n s 100n s
VALID
100n s 100n s
Ts/ 96
Ts/ 96
Ts/ 48
Ts/ 48
Alesis Semicon du ctor
DS1201-0702
12555 J efferson Blvd., Su ite 285
Los An geles, CA 90066
Ph one (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
- 6 -
ETC [ ETC ]
