U634H256
Disabling Automatic STORES: STORE Cycle Inhibit and Automatic Power Up RECALL
VCAP
5.0 V
VSWITCH
t
STORE inhibit
(24)
Power Up
RECALL
tRESTORE
Power
Supply
VCCX
HSB
VCAP
VCAP
VCCX
HSB
10 kΩ
Power
Supply
1
32
31
30
29
28
27
26
25
24
23
1
32
31
30
29
28
27
26
25
24
23
(optional,
2
2
see description HSB
nonvolatile store)
10 kΩ
3
3
(optional,
4
4
see description HSB
nonvolatile store)
5
5
6
6
+
7
7
8
8
100 µF
0.1 µF
0.1 µF
9
9
± 20 % Bypass
Bypass
10
10
11
12
13
14
15
16
11
12
13
14
15
16
22
21
20
19
18
17
22
21
20
19
18
17
VSS
VSS
Figure 1: Automatic STORE Operation
Figure 2: Disabling Automatic STORES
Schematic Diagram
Schematic Diagram
Low Average Active Power
The U634H256 has been designed to draw significantly
less power when E is LOW (chip enabled) but the
access cycle time is longer than 55 ns.
When E is HIGH the chip consumes only standby cur-
rent.
1. CMOS or TTL input levels
2. the time during which the chip is disabled (E HIGH)
3. the cycle time for accesses (E LOW)
4. the ratio of READs to WRITEs
5. the operating temperature
The overall average current drawn by the part depends
on the following items:
6. the power supply voltage level
The information describes the type of component and shall not be considered as assured characteristics. Terms of
delivery and rights to change design reserved.
13
April 21, 2004
ZMD [ Zentrum Mikroelektronik Dresden AG ]
