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U634H256SK35 参数 Datasheet PDF下载

U634H256SK35图片预览
型号: U634H256SK35
PDF下载: 下载PDF文件 查看货源
内容描述: POWERSTORE 32K ×8 NVSRAM [POWERSTORE 32K X 8 NVSRAM]
分类和应用: 内存集成电路静态存储器光电二极管
文件页数/大小: 14 页 / 248 K
品牌: ZMD [ Zentrum Mikroelektronik Dresden AG ]
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U634H256  
1.  
2.  
3.  
4.  
5.  
6.  
Read address  
Read address  
Read address  
Read address  
Read address  
Read address  
0E38 (hex) Valid READ  
31C7 (hex) Valid READ  
03E0 (hex) Valid READ  
3C1F (hex) Valid READ  
303F (hex) Valid READ  
0FC0 (hex) Initiate STORE  
the STORE operation will begin immediately.  
HARDWARE-STORE-BUSY (HSB) is a high speed,  
low drive capability bidirectional control line.  
In order to allow a bank of U634H256s to perform syn-  
chronized STORE functions, the HSB pin from a num-  
ber of chips may be connected together. Each chip  
contains a small internal current source to pull HSB  
HIGH when it is not being driven LOW. To decrease the  
sensitivity of this signal to noise generated on the PC  
board, it may optionally be pulled to power supply via  
an external resistor with a value such that the combi-  
ned load of the resistor and all parallel chip connections  
does not exceed IHSBOL at VOL (see Figure 1 and 2).  
Only if HSB is to be connected to external circuits, an  
external pull-up resistor should be used.  
Once the sixth address in the sequence has been  
entered, the STORE cycle will commence and the chip  
will be disabled. It is important that READ cycles and  
not WRITE cycles are used in the sequence, although it  
is not necessary that G is LOW for the sequence to be  
valid. After the tSTORE cycle time has been fulfilled, the  
SRAM will again be activated for READ and WRITE  
operation.  
During any STORE operation, regardless of how it was  
initiated, the U634H256 will continue to drive the HSB  
pin LOW, releasing it only when the STORE is com-  
plete.  
Software Nonvolatile RECALL  
A RECALL cycle of the EEPROM data into the SRAM  
is initiated with a sequence of READ operations in a  
manner similar to the STORE initiation. To initiate the  
RECALL cycle the following sequence of READ opera-  
tions must be performed:  
Upon completion of a STORE operation, the part will be  
disabled until HSB actually goes HIGH.  
Hardware Protection  
1.  
2.  
3.  
4.  
5.  
6.  
Read address  
Read address  
Read address  
Read address  
Read address  
Read address  
0E38 (hex) Valid READ  
31C7 (hex) Valid READ  
03E0 (hex) Valid READ  
3C1F (hex) Valid READ  
303F (hex) Valid READ  
0C63 (hex) Initiate RECALL  
The U634H256 offers hardware protection against  
inadvertent STORE operation during low voltage condi-  
tions. When VCAP < VSWITCH, all software or HSB initia-  
ted STORE operations will be inhibited.  
Preventing Automatic STORES  
Internally, RECALL is a two step procedure. First, the  
SRAM data is cleared and second, the nonvolatile  
information is transferred into the SRAM cells. The  
RECALL operation in no way alters the data in the  
EEPROM cells. The nonvolatile data can be recalled an  
unlimited number of times.  
The PowerStore function can be disabled on the fly by  
holding HSB HIGH with a driver capable of sourcing  
15 mA at VOH of at least 2.2 V as it will have to overpo-  
wer the internal pull-down device that drives HSB LOW  
for 50 ns at the onset of a PowerStore.  
When the U634H256 is connected for PowerStore ope-  
ration (see Figure 1) and VCCX crosses VSWITCH on the  
way down, the U634H256 will attempt to pull HSB  
LOW; if HSB doesnt actually get below VIL, the part will  
stop trying to pull HSB LOW and abort the PowerStore  
attempt.  
HSB Nonvolatile STORE  
The hardware controlled STORE Busy pin (HSB) is  
connected to an open drain circuit acting as both input  
and output to perform two different functions. When  
driven LOW by the internal chip circuitry it indicates that  
a STORE operation (initiated via any means) is in pro-  
gress within the chip. When driven LOW by external cir-  
cuitry for longer than tw(H)S, the chip will conditionally  
Disabling Automatic STORES  
If the PowerStore function is not required, then VCAP  
should be tied directly to the power supply and VCCX  
should by tied to ground. In this mode, STORE opera-  
tion may be triggered through software control or the  
HSB pin. In either event, VCAP (Pin 1) must always  
have a proper bypass capacitor connected to it (Figure  
2).  
initiate a STORE operation after tdis(H)S  
.
READ and WRITE operations that are in progress  
when HSB is driven LOW (either by internal or external  
circuitry) will be allowed to complete before the STORE  
operation is performed, in the following manner.  
After HSB goes LOW, the part will continue normal  
SRAM operation for tdis(H)S. During tdis(H)S, a transition  
on any address or control signal will terminate SRAM  
operation and cause the STORE to commence.  
Note that if an SRAM WRITE is attempted after HSB  
has been forced LOW, the WRITE will not occur and  
12  
April 21, 2004