Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
I
1
2
3
1
2
3
I
I
I
1
2
3
I
1
2
3
φ
1
A -A (A )
0
18
19
PC+1
PC
PC+1
4DH
PC
EDH
4DH
EDH
D -D
0
7
M1
MREQ
RD
ST
Figure 9. RETI Instruction Sequence with MIE=0
Table 4. RETI Control Signal States with MIE=0
Machine
Cycle States
M1
WR MREQ IORQ IOC=1 IOC=0 HALT
Address
Data
RD
ST
1
2
T1-T3
T1-T3
Ti
1st Opcode
2nd Opcode
NA
EDH
0
0
1
1
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
4DH
Tri-State
Tri-State
Tri-State
EDH
Ti
NA
Ti
NA
3
T1-T3
Ti
1st Opcode
NA
Tri-State
4DH
4
5
6
T1-T3
T1-T3
T1-T3
2nd Opcode
SP
Data
SP+1
Data
M1TE (M1 Temporary Enable). This bit controls the tem-
porary assertion of the /M1 signal. It is always read back
as a 1 and is set to 1 during reset.
For example, when a control word is written to the Z80 PIO
to enable interrupts, no enable actually takes place until
the PIO sees an active M1 signal. When M1TE=1, there is
no change in the operation of the /M1 signal and M1E con-
trols its function. When M1TE=0, the M1 output will be as-
serted during the next opcode fetch cycle regardless of the
state programmed into the M1E bit. This is only momen-
tary (one time) and the user need not preprogram a 1 to
disable the function (see Figure10).
When M1E is set to 0 to accommodate certain external
Z80 peripheral(s), those same device(s) may require a
pulse on M1 after programming certain of their registers to
complete the function being programmed.
DS971800401
P R E L I M I N A R Y
1-15
ZILOG [ ZILOG, INC. ]
