Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
Figure 15 shows the timing for exiting IDLE mode due to
Z80180/Z8S180/Z8L180 takes about 9.5 clocks to restart.
an
interrupt
request.
Note
that
the
1
Opcode Fetch or Interrupt
Acknowledge Cycle
IDLE Mode
T
T
4
T
T
3
2
1
φ
9.5 Cycle Delay from INTi Asserted
NMI
or
INTi
A -A
19
0
FFFFFH
HALT
M1
Figure 15. Z80180/Z8S180/Z8L180 IDLE Mode Exit due to External Interrupt
While the Z80180/Z8S180/Z8L180 is in IDLE mode, it will
grant the bus to an external master if the BREXT bit
(CCR5) is 1. Figure 16 shows the timing for this sequence.
Note that the part takes 8 clock cycles longer to respond to
the Bus Request than in normal operation.
After the external master negates the Bus Request, the
Z80180/Z8S180/Z8L180 disables the PHI clock and re-
mains in IDLE mode.
DS971800401
P R E L I M I N A R Y
1-19
ZILOG [ ZILOG, INC. ]
