Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
/NMI. Non-maskable Interrupt (Input, negative edge trig-
gered). /NMI has a higher priority than /INT and is always
recognized at the end of an instruction, regardless of the
state of the interrupt enable flip-flops. This signal forces
CPU execution to continue at location 0066H.
TOUT. Timer Out (Output, active High). T
output from PRT channel 1. This line is multiplexed with
A18 of the address bus.
is the pulse
OUT
1
TXA0, TXA1. Transmit Data 0 and 1 (Outputs, active
High). These signals are the transmitted data from the
ASCI channels. Transmitted data changes are with re-
spect to the falling edge of the transmit clock.
/RD. ReOpcoded (Output, active Low, tri-state). /RD indi-
cated that the CPU wants to read data from memory or an
I/O device. The addressed I/O or memory device should
use this signal to gate data onto the CPU data bus.
TXS. Clocked Serial Transmit Data (Output, active High).
This line is the transmitted data from the CSIO channel.
/RFSH. Refresh (Output, active Low). Together with
/MREQ, /RFSH indicates that the current CPU machine
cycle and the contents of the address bus should be used
for refresh of dynamic memories. The low order 8 bits of
the address bus (A7 - A10) contain the refresh address.
This signal is analogous to the /REF signal of the
Z64180.
/WAIT. Wait (Input, active Low). /WAIT indicated to the
MPU that the addressed memory or I/O devices are not
ready for a data transfer. This input is sampled on the fall-
ing edge of T2 (and subsequent wait states). If the input is
sampled Low, then the additional wait states are inserted
until the /WAIT input is sampled high, at which time execu-
tion will continue.
/RTS0. Request to Send 0 (Output, active Low). This is a
programmable modem control signal for ASCI channel 0.
/WR. Write (Output, active Low, tri-state). /WR indicated
that the CPU data bus holds valid data to be stored at the
addressed I/O or memory location.
RXA0, RXA1. Receive Data 0 and 1 (Input, active High).
These signals are the receive data to the ASCI channels.
XTAL. Crystal (Input, active High). Crystal oscillator con-
nection. This pin should be left open if an external clock is
used instead of a crystal. The oscillator input is not a TTL
level (reference DC characteristics).
RXS. Clocked Serial Receive Data (Input, active High).
This line is the receiver data for the CSIO channel. RXS is
multiplexed with the /CTS1 signal for ASCI channel 1.
ST. Status (Output, active High). This signal is used with
the /M1 and /HALT output to decode the status of the CPU
machine cycle.
Several pins are used for different conditions, depending
on the circumstance.
Multiplexed Pin Descriptions
Table 3. Status Summary
A18 / /T
During RESET, this pin is initialized as
A18 pin. If either TOC1 or TOC0 bit of
the Timer Control Register (TCR) is set
to 1, TOUT function is selected. If
TOC1 and TOC0 are cleared to 0, A18
function is selected.
OUT
ST
Operation
/HALT /M1
0
1
1
1
0
0
1
CPU Operation
(1st opcode fetch)
1
1
CPU Operation (2nd opcode and
3rd Opcode fetch)
CPU Operation
(MC except for Opcode fetch)
CKA0 / /DREQ0 During RESET, this pin is initialized as
CKA0 pin. If either DM1 or SM1 in
DMA Mode Register (DMODE) is set to
1, /DREQ0 function is always selected.
0
0
1
X
0
0
1
0
1
DMA Operation
HALT Mode
CKA1 / /TEND0 During RESET, this pin is initialized as
CKA1 pin. If CKA1D bit in ASCI control
register ch1 (CNTLA1) is set to 1,
/TEND0 function is selected. If CKA1D
bit is set to 0, CKA1 function is
SLEEP Mode
(including SYSTEM STOP Mode)
Notes:
X = Reserved
MC = Machine Cycle
selected.
RXS / /CTS1
During RESET, this pin is initialized as
RXS pin. If CTS1E bit in ASCI status
/TEND0, /TEND1. Transfer End 0 and 1 (Outputs, active
Low). This output is asserted active during the last write
cycle of a DMA operation. It is used to indicate the end of
the block transfer. /TEND0 is multiplexed with CKA1.
register ch1 (STAT1) is set to 1, /CTS
1
function is selected. If CTS1E bit is set
to 0, RXS function is selected.
TEST. Test (Output, not in DIP version). This pin is for test
and should be left open.
DS971800401
P R E L I M I N A R Y
1-11
ZILOG [ ZILOG, INC. ]
