Z80180/Z8S180/Z8L180
Enhanced Z180 Microprocessor
Zilog
T
T
T
T
T
T
3
1
2
3
1
2
φ
/WR
/M1
Write into OMCR
Opcode Fetch
Figure 10. M1 Temporary Enable Timing
IOC. This bit controls the timing of the /IORQ and /RD sig-
nals. It is set to 1 by reset.
When /IOC=1, the /IORQ and /RD signals function the
same as the Z64180 (Figure 11).
T
T
T
T
3
1
2
W
φ
/IORQ
/RD
/WR
Figure 11. I/O Read and Write Cycles with IOC = 1
When /IOC = 0, the timing of the /IORQ and RD signals
match the timing of the Z80. The /IORQ and /RD signals
go active as a result of the rising edge of T2. (Figure 12.)
T
T
T
T
3
1
2
W
φ
/IORQ
/RD
/WR
Figure 12. I/O Read and Write Cycles with IOC = 0
1-16
P R E L I M I N A R Y
DS971800401
ZILOG [ ZILOG, INC. ]
