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ZiLOG
//7ꢄ%1//10ꢄ$#5'ꢄ4')+56'4
The Common Base Register (%$4) specifies the base ad-
dress (on 4-KB boundaries) used to generate a 20-bit phys-
ical address for Common Area 1 accesses. All bits of %$4
are reset toꢅ0during 4'5'6.
//7ꢄ%QOOQPꢄ$CUGꢄ4GIKUVGT
/PGOQPKEꢄ%$4
#FFTGUUꢄꢋꢀ*
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(KIWTG ꢐꢀꢆ //7ꢄ%QOOQPꢄ$CUGꢄ4GIKUVGTꢄꢌ%$4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢀ*ꢍ
//7ꢄ$#0-ꢄ$#5'ꢄ4')+56'4
The Bank Base Register ($$4) specifies the base address
(on 4-KB boundaries) used to generate a 20-bit physical ad-
dress for Bank Area accesses. All bits of $$4 are reset to
0during 4'5'6.
//7ꢄ$CPMꢄ$CUGꢄ4GIKUVGT
/PGOQPKEꢄ$$4
#FFTGUUꢄꢋꢏ*
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(KIWTG ꢐꢏꢆ //7ꢄ$CPMꢄ$CUGꢄ4GIKUVGTꢄꢌ$$4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋꢏ*ꢍ
//7ꢄ%1//10ꢃ$#0-ꢄ#4'#ꢄ4')+56'4
TheCommon/BankAreaRegister(%$#4)specifiesbound-
aries within the Z8S180/Z8L180 64-KB logical address
space for up to three areas; Common Area), Bank Area and
Common Area 1.
//7ꢄ%QOOQPꢃ$CPMꢄ#TGCꢄ4GIKUVGT
/PGOQPKEꢄ%$#4
#FFTGUUꢄꢋ#*
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(KIWTG ꢀꢂꢆ //7ꢄ%QOOQPꢃ$CPMꢄ#TGCꢄ4GIKUVGTꢄꢌ%$#4ꢅꢄ+ꢃ1ꢄ#FFTGUUꢄꢒꢄꢋ#*ꢍ
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