Z8FMC16100 Series Flash MCU
Product Specification
65
Following completion of the Stop-Mode Recovery the eZ8 CPU responds to the system
exception request by fetching the System Exception vector and executing code from the
vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watch-Dog Timer forces the
device into the Reset state. The WDTstatus bit in the Reset Status and Control Register is
set to 1. Refer to the Reset and Stop-Mode Recovery chapter on page 23 for more informa-
tion on Reset and the WDTstatus bit. Following a Reset sequence, the WDT Counter is ini-
tialized with its reset value.
WDT Reset in Stop Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the Watch-Dog Timer initiates a Stop-Mode Recovery. Both
the WDTstatus bit and the STOPbit in the Reset Status and Control Register are set to 1
following WDT time-out in STOP mode. Refer to the Reset and Stop-Mode Recovery
chapter on page 23 for more information.
Watch-Dog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watch-Dog Timer Reload High (WDTH) Register
address unlocks the two Watch-Dog Timer Reload registers (WDTH and WDTL) to allow
changes to the time-out period. These write operations to the WDTH register address pro-
duce no effect on the bits in the WDTH register. The locking mechanism prevents spurious
writes to the Reload registers. The following sequence is required to unlock the Watch-
Dog Timer Reload registers (WDTH and WDTL) for write access.
1. Write 55Hto the Watch-Dog Timer Reload High register (WDTH).
2. Write AAHto the Watch-Dog Timer Reload High register (WDTH).
3. Write the appropriate value to the Watch-Dog Timer Reload High register (WDTH).
4. Write the appropriate value to the Watch-Dog Timer Reload Low register (WDTL).
All steps of the Watch-Dog Timer Reload Unlock sequence must be written in the order
just listed. The value in the Watch-Dog Timer Reload registers is loaded into the counter
every time a WDTinstruction is executed.
Watch-Dog Timer Reload High and Low Byte Registers
The Watch-Dog Timer Reload High and Low Byte (WDTH, WDTL) registers, shown in
Table 40 through Table 41, form the 16-bit reload value that is loaded into the Watch-Dog
Timer when a WDTinstruction executes. The 16-bit reload value is {WDTH[7:0],
WDTL[7:0]}. Writing to these registers following the unlock sequence sets the appropri-
PS024604-1005
P R E L I M I N A R Y
Watch-Dog Timer Reload Unlock Sequence
ZILOG [ ZILOG, INC. ]
