Z8FMC16100 Series Flash MCU
Product Specification
61
Bit
Name
Description
Position
[3]
[2]
[1]
[0]
PA73ENL Port A73 Interrupt Request Enable Low Bit
PA62ENL Port A62 Interrupt Request Enable Low Bit
PA51ENL Port A51 Interrupt Request Enable Low Bit
PA40ENL Port A40 Interrupt Request Enable Low Bit
Interrupt Control Register
The Interrupt Control (IRQCTL) Register, shown in Table 38, contains the Master Enable
Bit (IRQE) for all interrupts.
Table 38. Interrupt Control Register (IRQCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
IRQE
Reserved
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
FCFH
ADDR
IRQE—Interrupt Request Enable
This bit is set to 1 by execution of an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request or system exception,
Reset, or direct register write to 0.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0.
PS024604-1005
P R E L I M I N A R Y
Interrupt Control Register
ZILOG [ ZILOG, INC. ]
