Z8 Encore!® Motor Control Flash MCUs
Product Specification
58
Bit
Value
(H)
Description
Position
[1]
PA5 or PA1 Interrupt Request — Logic in the Port A GPIO module selects either
PA5 or PA1 and either rising or falling edge.
PA51I
0
1
No interrupt request is pending for PA5 or PA1
An interrupt request from PA5 or PA1 is awaiting service.
[0]
PA4 or PA0 Interrupt Request — Logic in the Port A GPIO module selects either
PA4 or PA0 and either rising or falling edge.
PA40I
0
1
No interrupt request is pending for PA4 or PA0
An interrupt request from PA4 or PA0 is awaiting service.
IRQ0 Enable High and Low Bit Registers
The IRQ0 Enable High and Low Bit registers, shown in Tables 33 and 34, form a priority
encoded enabling for interrupts in the Interrupt Request 0 Register. Priority is generated
by setting bits in each register. Table 32 describes the priority control for IRQ0.
Table 32. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
Note: x indicates the register bits from 0 through 7.
Table 33. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
PWMENH FLTENH ADCENH CMPENH
T0ENH
U0RENH U0TENH SPIENH
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC1H
ADDR
PWMENH—Pulse-Width Modulator Interrupt Request Enable High Bit
FLTENH—Fault Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
CMPENH—Comparator Interrupt Request Enable High Bit
Interrupt Controller
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
