Z8FMC16100 Series Flash MCU
Product Specification
275
Figure 55 and Table 153 provide timing information for UART pins for the case where the
Clear To Send input signal (CTS) is not used for flow control. In this example, it is
assumed that the Driver Enable polarity has been configured to be Active Low and is rep-
resented here by DE. DE asserts after the UART Transmit Data Register has been written.
DE remains asserted for multiple characters as long as the Transmit Data Register is writ-
ten with the next character before the current character has completed.
DE
(Output)
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T1
T2
TxD
(Output)
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Start Bit 0 Bit 1
Bit 7 Parity Stop
End of
Stop Bit(s)
Figure 55. UART Timing without CTS
Table 153. UART Timing without CTS
Delay (ns)
Minimum Maximum
1 bit period 1 bit period +
Parameter Abbreviation
T
DE assertion to TxD falling edge (start)
delay
1
1 x X period
IN
T
End of stop bit(s) to DE deassertion delay 1 x X period 2 x X period
2
IN
IN
PS024604-1005
P R E L I M I N A R Y
UART Timing
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