Z8FMC16100 Series Flash MCU
Product Specification
279
The size of the register file varies depending upon device type. The register file is 512
bytes for the Z8FMC16100 Series Flash MCU.
Note:
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that is
described in Table 154.
.
Table 154. Notational Shorthand
Notation Description
Operand Range
b
Bit
b
b represents a value from 0 to 7 (000b to 111b).
cc
Condition Code
—
See Condition Codes overview in the eZ8 CPU
User Manual (UM0128).
DA
ER
Direct Address
Addrs
Addrs represents a number in the range of 0000h
to FFFFh.
Extended Addressing Register Reg
Reg. represents a number in the range of 000h to
FFFh.
IM
Ir
Immediate Data
#Data
Data is a number between 00h to FFh.
n = 0 –15.
Indirect Working Register
Indirect Register
@Rn
IR
@Reg
Reg. represents a number in the range of 00h to
FFh.
Irr
Indirect Working Register Pair @RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14.
IRR
Indirect Register Pair
@Reg
Reg. represents an even number in the range 00h
to FEh.
p
Polarity
p
Polarity is a single bit binary value of either 0b or
1b.
r
Working Register
Register
Rn
n = 0–15.
R
Reg
Reg. represents a number in the range of 00h to
FFh.
RA
Relative Address
X
X represents an index in the range of +127 to
–128, which is an offset relative to the address of
the next instruction.
rr
Working Register Pair
Register Pair
RRp
Reg
p = 0, 2, 4, 6, 8, 10, 12, or 14.
RR
Reg. represents an even number in the range of
00h to FEh.
PS024604-1005
P R E L I M I N A R Y
eZ8 CPU Instruction Set
ZILOG [ ZILOG, INC. ]
