Z8FMC16100 Series Flash MCU
Product Specification
271
General Purpose I/O Port Input Data Sample Timing
Figure 51 illustrates the timing of the GPIO Port input sampling. Table 149 lists the GPIO
port input timing.
TCLK
System
Clock
Port Value
Changes to 0
GPIO Pin
Input Value
GPIO Input
Data Latch
0 Latched
into Port Input
Data Register
GPIO Data Register
Value 0 Read
by eZ8 CPU
GPIO Data
Read on Data Bus
Figure 51. Port Input Sample Timing
Table 149 and Table 150 provide timing information for the GPIO Port inputs and outputs.
Table 149. GPIO Port Input Timing
Delay (ns)
Parameter Abbreviation
Min
Max
T
Port input transition to X fall setup time
5
—
S_PORT
IN
(Not pictured)
T
T
X
fall to port input transition hold time (not pictured).
IN
5
—
H_PORT
SMR
GPIO port pin pulse width to ensure Stop-Mode
Recovery (for GPIO port pins enabled as SMR
sources) .
1µs
PS024604-1005
P R E L I M I N A R Y
General Purpose I/O Port Input Data Sample
ZILOG [ ZILOG, INC. ]
