Z8FMC16100 Series Flash MCU
Product Specification
273
On-Chip Debugger Timing
Figure 53 and Table 151 provide timing information for the DBG pin. The DBG pin tim-
ing specifications assume a 4µs maximum rise and fall time.
TCLK
XIN
DBG Output
Output Data
T1
T2
T4
DBG Input
Input Data
T3
Figure 53. On-Chip Debugger Timing
Table 151. On-Chip Debugger Timing
Delay (ns)
Minimum Maximum
Parameter Abbreviation
T
T
T
T
X
X
Rise to DBG Valid Delay
—
2
15
—
—
—
1
2
3
4
IN
IN
Rise to DBG Output Hold Time
DBG to X Rise Input Setup Time
10
5
IN
DBG to X Rise Input Hold Time
IN
DBG Frequency
System
Clock ÷ 4
PS024604-1005
P R E L I M I N A R Y
On-Chip Debugger Timing
ZILOG [ ZILOG, INC. ]
