Z8FMC16100 Series Flash MCU
Product Specification
163
2
I C Master/Slave Controller
The I2C Master/Slave Controller ensures that the Z8FMC16100 Series Flash MCU
devices are bus-compatible with the I2C protocol. The I2C bus consists of the serial data
signal (SDA) and a serial clock signal (SCL) bidirectional lines. Features of the I2C con-
troller include:
•
•
•
•
•
•
•
Operates in MASTER/SLAVE or SLAVE ONLY modes
Supports arbitration in a multimaster environment (MASTER/SLAVE mode)
Supports data rates up to 400Kbps
7- or 10-bit slave address recognition (interrupt only on address match)
Optional general call address recognition
Optional digital filter on receive SDA, SCL lines
Optional interactive receive mode allows software interpretation of each received ad-
dress and/or data byte before acknowledging
•
•
Unrestricted number of data bytes per transfer
Baud Rate Generator can be used as a general-purpose timer with an interrupt if the I2C
controller is disabled.
Architecture
Figure 27 illustrates the architecture of the I2C controller.
PS024604-1005
P R E L I M I N A R Y
Architecture
ZILOG [ ZILOG, INC. ]
