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Z8FMC04100QKSG 参数 Datasheet PDF下载

Z8FMC04100QKSG图片预览
型号: Z8FMC04100QKSG
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采-R电机控制闪存MCU [Z8 Encore-R Motor Control Flash MCUs]
分类和应用: 闪存微控制器和处理器外围集成电路电机时钟
文件页数/大小: 402 页 / 4558 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore!® Motor Control Flash MCUs  
Product Specification  
166  
The I2CSLVAD Register is added to provide programming capabilities for the slave  
address.  
The ACKV bit in the I2CSTATE Register enables the master to check the Acknowl-  
edge from the slave before sending the next byte.  
Support for multimaster environments—if arbitration is lost when operating as a mas-  
ter, the ARBLST bit in the I2CISTAT Register is set and the mode automatically  
switches to SLAVE mode.  
Operation  
The I2C Master/Slave Controller operates in MASTER/SLAVE mode, SLAVE ONLY  
mode, or with master arbitration. In MASTER/SLAVE mode, it can be used as the only  
master on the bus or as one of several masters on the bus, with arbitration. In a multimaster  
environment, the controller switches from MASTER to SLAVE mode upon losing arbitra-  
tion.  
Though slave operation is fully supported in MASTER/SLAVE mode, if a device is  
intended to operate only as a slave, then SLAVE ONLY mode can be selected. In SLAVE  
ONLY mode, the device will not initiate a transaction, even if the software inadvertently  
sets the START bit.  
SDA and SCL Signals  
The I2C circuit sends all addresses, data, and Acknowledge signals over the SDA line,  
most-significant bit first. SCL is the clock for the I2C bus. When the SDA and SCL pin  
alternate functions are selected for their respective GPIO ports, the pins are automatically  
configured for open-drain operation.  
The master is responsible for driving the SCL clock signal. During the Low period of the  
clock, a slave can hold the SCL signal Low to suspend the transaction if it is not ready to  
proceed. The master releases the clock at the end of the Low period and notices that the  
clock remains Low instead of returning to a High level. When the slave releases the clock,  
the I2C master continues the transaction. All data is transferred in bytes; there is no limit to  
the amount of data transferred in one operation. When transmitting address, data, or an  
Acknowledge, the SDA signal changes in the middle of the Low period of SCL. When  
receiving address, Data or an Acknowledge, the SDA signal is sampled in the middle of  
the High period of SCL.  
A low-pass digital filter can be applied to the SDA and SCL receive signals by setting the  
Filter Enable (FILTEN) bit in the I2C Control Register. When the filter is enabled, any  
glitch that is less than a system clock period in width will be rejected. This filter should be  
enabled when running in I2C FAST mode (400kbps), and can also be used at lower data  
rates.  
I2C Master/Slave Controller  
P R E L I M I N A R Y  
PS024604-1005