Z8 Encore!® Motor Control Flash MCUs
Product Specification
136
of the LIN Control register. One or two stop bits are automatically provided by the hard-
ware in LIN mode as defined by the STOPbit.
0 = No break is sent.
1 = The output of the transmitter is 0.
STOP—Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
LBEN—Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver within the IrDA module.
LIN-UART Control 1 Registers
Multiple registers, shown in Tables 72 through 74) are accessible by a single bus address.
The register selected is determined by the Mode Select (MSEL) field. These registers pro-
vide additional control over LIN-UART operation.
Multiprocessor Control Register
When MSEL = 000b, the Multiprocessor Control Register, shown in Table 72, provides
control for UART multiprocessor mode, IRDA mode, baud rate timer mode as well as other
features that may apply to multiple modes. A more detailed discussion of each bit follows
the table.
Table 72. MultiProcessor Control Register (U0CTL1 with MSEL = 000b)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
MPMD[1]
MPEN
MPMD[0]
MPBT
DEPOL BRGCTL
RDAIRQ
IREN
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F43H with MSEL= 000b
ADDR
MPMD[1:0]—Multiprocessor Mode
If MULTIPROCESSOR (9-bit) mode is enabled,
00 = The LIN-UART generates an interrupt request on all received bytes (data and
address).
01 = The LIN-UART generates an interrupt request only on received address bytes.
10 = The LIN-UART generates an interrupt request when a received address byte matches
the value stored in the Address Compare Register and on all successive data bytes until an
address mismatch occurs.
LIN-UART
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
