Z8 Encore!® Motor Control Flash MCUs
Product Specification
132
nal to provide flow control in loopback mode. CTS only affects transmission if the CTSE
bit = 1.
Table 69. LIN-UART Status 0 Register - LIN mode (U0STAT0)
7
BITS
FIELD
RESET
R/W
6
5
4
3
2
1
0
RDA
PLE
ABOE
FE
BRKD
TDRE
TXE
ATB
0
0
0
0
0
1
1
0
R
R
R
R
R
R
R
R
F41H
ADDR
Receive Data Available (RDA). This bit indicates that the Receive Data Register has
received data. Reading the Receive Data Register clears this bit.
Physical Layer Error (PLE). This bit indicates that transmit and receive data do not
match when a LIN slave or master is transmitting. This could be caused by a fault in the
physical layer or multiple devices driving the bus simultaneously. Reading the Status 0
Register or the Receive Data Register clears this bit.
Receive Data and Autobaud Overrun Error (OE). This bit is set just as in normal UART
operation if a receive data overrun error occurs. This bit is also set during LIN Slave auto-
baud if the BRG counter overflows before the end of the autobaud sequence, indicating
the receive activity was not an autobaud character or the master baud rate is too slow. The
ATB status bit will also be set in this case. This bit is cleared by reading the Receive Data
Register.
Framing Error (FE). This bit indicates that a framing error (no STOP bit following data
reception) was detected. Reading the Receive Data Register clears this bit.
Break Detect (BRKD). This bit is set in LIN mode if (a) in LinSleep state and a break of at
least 4 bit times occurred (Wake-up event) or (b) in Slave Wait Break state and a break of
at least 11 bit times occurred (Break event) or (c) in Slave Active state and a break of at
least 10 bit times occurs. Reading the Status 0 Register or the Receive Data Register clears
this bit.
Transmitter Data Register Empty (TDRE). This bit indicates that the Transmit Data
Register is empty and ready for additional data. Writing to the Transmit Data Register
resets this bit.
Transmitter Empty (TXE). This bit indicates that the transmit shift register is empty and
character transmission is finished.
LIN Slave Autobaud Complete (ATB). This bit is set in LIN SLAVE mode when an auto-
baud character is received. If the ABIEN bit is set in the LIN Control Register, then a
LIN-UART
P R E L I M I N A R Y
PS024604-1005
ZILOG [ ZILOG, INC. ]
