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Z8FMC04100QKSG 参数 Datasheet PDF下载

Z8FMC04100QKSG图片预览
型号: Z8FMC04100QKSG
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采-R电机控制闪存MCU [Z8 Encore-R Motor Control Flash MCUs]
分类和应用: 闪存微控制器和处理器外围集成电路电机时钟
文件页数/大小: 402 页 / 4558 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore!® Motor Control Flash MCUs  
Product Specification  
134  
NEWFRM—Status bit denoting the start of a new frame. Reading the LIN-UART Receive  
Data register resets this bit to 0.  
0 = The current byte is not the first data byte of a new frame.  
1 = The current byte is the first data byte of a new frame.  
MPRX—Multiprocessor Receive  
Returns the value of the last multiprocessor bit received. Reading from the LIN-UART  
Receive Data register resets this bit to 0.  
Digital Noise Filter Mode Status Field (MSEL = 001B)  
NE—Noise Event. This bit is asserted if digital noise is detected on the receive data line  
while the data is sampled (center of bit time). If this bit is set, it does not mean that the  
receive data is corrupted (though it may be in extreme cases), just that one or more of the  
noise filter data samples near the center of the bit time did not match the average data  
value.  
LIN Mode Status Field (MSEL = 010B)  
NE—Noise Event. This bit is asserted if some noise level is detected on the receive data  
line while the data is sampled (center of bit time). If this bit is set, it does not indicate that  
the receive data is corrupt (though it may be in extreme cases), just that one or more of the  
16x data samples near the center of the bit time did not match the average data value.  
RxBreakLength—LIN mode received break length. This field may be read following a  
break (LIN WAKE-UP or BREAK) so software can determine the measured duration of  
the break. If the break exceeds 15 bit times the value saturates at 1111B.  
Hardware Revision Mode Status Field (MSEL = 111B)  
This field indicates the hardware revision of the LIN-UART block.  
00_xxx LIN UART hardware rev  
01_xxx reserved  
10_xxx reserved  
11_xxx reserved  
LIN-UART Control 0 Register  
The LIN-UART Control 0 Register, shown in Table 71, configures the basic properties of  
the LIN-UART’s transmit and receive operations. A more detailed discussion of each bit  
follows the table.  
LIN-UART  
P R E L I M I N A R Y  
PS024604-1005  
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