Z8FMC16100 Series Flash MCU
Product Specification
133
receive interrupt is generated when this bit is set. Reading the Status 0 Register clears this
bit. This bit will be 0 in LIN MASTER mode.
LIN-UART Mode Select and Status Register
The LIN-UART Mode Select and Status Register, shown in Table 70, contains mode select
and status bits. A more detailed discussion of each bit follows the table.
Table 70. LIN-UART Mode Select and Status Register (U0MDSTAT)
7
BITS
FIELD
RESET
R/W
6
5
4
3
2
1
0
MSEL
Mode Status
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
F44H
ADDR
MSEL—Mode Select.
This R/W field determines which control register is accessed when performing a write or
read to the Uart Control 1 Register address. This field also determines which status is
returned in the ModeStatus field when reading this register.
000 = Multiprocessor and normal UART control/status
001 = Noise Filter control/status
010 = LIN Protocol control/status
011–110: reserved
111 = LIN-UART Hardware Revision (allows hardware revision to be read in the Mode
Status field)
Mode Status. This read-only field returns status corresponding to the mode selected by
MSELas follows
000 : Multiprocessor and normal UART mode status = {NE, 0, 0, NEWFRM, MPRX}
001 : Noise Filter status = {NE, 0,0,0,0}
010 : LIN mode status = {NE, RxBreakLength[3:0]}
011–110 : reserved = {0, 0, 0, 0, 0}
111 : LIN-UART hardware revision
MULTIPROCESSOR Mode Status field (MSEL = 000B)
NE—Noise Event. This bit is asserted if digital noise is detected on the receive data line
while the data is sampled (center of bit time). If this bit is set, it does not mean that the
receive data is corrupted (though it may be in extreme cases), just that one or more of the
noise filter data samples near the center of the bit time did not match the average data
value.
PS024604-1005
P R E L I M I N A R Y
LIN-UART Mode Select and Status Register
ZILOG [ ZILOG, INC. ]
