Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
98
16-clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RXD
min. 1.6
pulse
µs
UART’s
RXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
8-clock
delay
16-clock
period
16-clock
period
16-clock
period
16-clock
period
Figure 73. Infrared Data Reception
Jitter
Because of the inherent sampling of the received IR_RXD signal by the bit rate clock,
some jitter can be expected on the first bit in any sequence of data. All subsequent bits in
the received data stream are a fixed 16-clock periods wide.
Infrared Encoder/Decoder Control Register Definitions
All Infrared Endec configuration and status information is set by the UART control regis-
ters as defined beginning on page 86.
Caution:
To prevent spurious signals during IrDA data transmission, set the IREN
bit in the UARTx Control 1 register to 1 to enable the Infrared Encoder/
Decoder before enabling the GPIO Port alternate function for the corre-
sponding pin.
PS017610-0404
Infrared Encoder/Decoder
ZILOG [ ZILOG, INC. ]
