Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
164
OCD Watchpoint Address Register
The OCD Watchpoint Address register specifies the lower 8 bits of the Register File
address bus to match when generating Watchpoint Debug Breaks. The full 12-bit Register
File address is given by {WPTCTL3:0], WPTADDR[7:0]}.
Table 97. OCD Watchpoint Address (WPTADDR)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WPTADDR[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WPTADDR[7:0]—Watchpoint Register File Address
These bits specify the lower eight bits of the register address to match when generating a
Watchpoint Debug Break.
OCD Watchpoint Data Register
The OCD Watchpoint Data register specifies the data to match if Watchpoint data match is
enabled.
Table 98. OCD Watchpoint Data (WPTDATA)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WPTDATA[7:0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WPTDATA[7:0]—Watchpoint Register File Data
These bits specify the Register File data to match when generating Watchpoint Debug
Breaks with the WPDMbit (WPTCTL[5]) is set to 1.
—————
PS017610-0404
On-Chip Debugger
ZILOG [ ZILOG, INC. ]
