Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
162
BRKEN—Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00H). By default, Break-
points are disabled and the BRK instruction behaves like a NOP. If this bit is set to 1, when
a BRK instruction is decoded, the DBGMODEbit of the OCDCTL register is automatically
set to one.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
an Debug Acknowledge character (FFH) to the host when a Breakpoint or Watchpoint
occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
Reserved
These bits are reserved and must be 0.
RST—Reset
Setting this bit to 1 resets the Z8F640x family device. The device goes through a normal
Power-On Reset sequence with the exception that the On-Chip Debugger is not reset. This
bit is automatically cleared to 0 when the reset finishes.
0 = No effect.
1 = Reset Z8F640x family device.
OCD Status Register
The OCD Status register reports status information about the current state of the debugger
and the Z8F640x family device.
Table 95. OCD Status Register (OCDSTAT)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DBG
HALT
RPEN
Reserved
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
DBG—Debug Status
0 = The Z8F640x family device is operating in normal mode.
1 = The Z8F640x family device is in Debug mode.
HALT—Halt Mode
0 = The Z8F640x family device is not in Halt mode.
1 = The Z8F640x family device is in Halt mode.
PS017610-0404
On-Chip Debugger
ZILOG [ ZILOG, INC. ]
