Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
161
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Write Watchpoint (20H)—The Write Watchpoint command sets and configures the
debug Watchpoint. If the Z8F640x family device is not in Debug mode or the Read
Protect Option Bit is enabled, the WPTCTLbits are all set to zero.
DBG <-- 20H
DBG <-- WPTCTL[7:0]
DBG <-- WPTADDR[7:0]
DBG <-- WPTDATA[7:0]
Read Watchpoint (21H)—The Read Watchpoint command reads the current
Watchpoint registers.
DBG <-- 21H
DBG --> WPTCTL[7:0]
DBG --> WPTADDR[7:0]
DBG --> WPTDATA[7:0]
On-Chip Debugger Control Register Definitions
OCD Control Register
The OCD Control register controls the state of the On-Chip Debugger. This register enters
or exits Debug mode and enables the BRK instruction. It can also reset the Z8F640x fam-
ily device.
A “reset and stop” function can be achieved by writing 81Hto this register. A “reset and
go” function can be achieved by writing 41Hto this register. If the Z8F640x family device
is in Debug mode, a “run” function can be implemented by writing 40Hto this register.
Table 94. OCD Control Register (OCDCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
DBGMODE
BRKEN
DBGACK
Reserved
RST
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R/W
DBGMODE—Debug Mode
Setting this bit to 1 causes the Z8F640x family device to enter Debug mode. When in
Debug mode, the eZ8 CPU stops fetching new instructions. Clearing this bit causes the
eZ8 CPU to start running again. This bit is automatically set when a BRK instruction is
decoded and Breakpoints are enabled or when a Watchpoint Debug Break is detected. If
the Read Protect Option Bit is enabled, this bit can only be cleared by resetting the
Z8F640x family device, it cannot be written to 0.
0 = The Z8F640x family device is operating in normal mode.
1 = The Z8F640x family device is in Debug mode.
PS017610-0404
On-Chip Debugger
ZILOG [ ZILOG, INC. ]
