Z8F640x/Z8F480x/Z8F320x/Z8F240x/Z8F160x
Z8 Encore!®
163
RPEN—Read Protect Option Bit Enabled
0 = The Read Protect Option Bit is disabled (1).
0 = The Read Protect Option Bit is enabled (0), disabling many OCD commands.
Reserved
These bits are always 0.
OCD Watchpoint Control Register
The OCD Watchpoint Control register is used to configure the debug Watchpoint.
Table 96. OCD Watchpoint Control/Address (WPTCTL)
BITS
FIELD
RESET
R/W
7
6
5
4
3
2
1
0
WPW
WPR
WPDM
Reserved
WPTADDR[11:8]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WPW—Watchpoint Break on Write
This bit cannot be set if the Read Protect Option Bit is enabled.
0 = Watchpoint Break on Register File write is disabled.
1 = Watchpoint Break on Register File write is enabled.
WPR—Watchpoint Break on Read
This bit cannot be set if the Read Protect Option Bit is enabled.
0 = Watchpoint Break on Register File read is disabled.
1 = Watchpoint Break on Register File write is enabled.
WPDM—Watchpoint Data Match
If this bit is set, then the Watchpoint only generates a Debug Break if the data being read
or written matches the specified Watchpoint data. Either the WPRand/or WPWbits must
also be set for this bit to affect operation. This bit cannot be set if the Read Protect Option
Bit is enabled.
0 = Watchpoint Break on read and/or write does not require a data match.
1 = Watchpoint Break on read and/or write requires a data match.
Reserved
This bit is reserved and must be 0.
RADDR[11:8]—Register address
These bits specify the upper 4 bits of the Register File address to match when generating a
Watchpoint Debug Break. The full 12-bit Register File address is given by {WPTCTL3:0],
WPTADDR[7:0]}.
PS017610-0404
On-Chip Debugger
ZILOG [ ZILOG, INC. ]
