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Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
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Z8 Encore! XP® F08xA Series  
Product Specification  
80  
Table 55. Watch-Dog Timer Approximate Time-Out Delays  
Approximate Time-Out Delay  
(with 10KHz typical WDT oscillator frequency)  
WDT Reload Value  
(Hex)  
WDT Reload Value  
(Decimal)  
Typical  
400 µs  
Description  
000004  
FFFFFF  
4
Minimum time-out delay  
Maximum time-out delay  
16,777,215  
28 minutes  
Watch-Dog Timer Refresh  
When first enabled, the Watch-Dog Timer is loaded with the value in the Watch-Dog  
Timer Reload registers. The Watch-Dog Timer counts down to 000000Hunless a WDT  
instruction is executed by the eZ8 CPU. Execution of the WDT instruction causes the  
downcounter to be reloaded with the WDT Reload value stored in the Watch-Dog Timer  
Reload registers. Counting resumes following the reload operation.  
When the Z8 Encore! XP® F08xA Series devices are operating in DEBUG Mode (using  
the On-Chip Debugger), the Watch-Dog Timer is continuously refreshed to prevent any  
Watch-Dog Timer time-outs.  
Watch-Dog Timer Time-Out Response  
The Watch-Dog Timer times out when the counter reaches 000000H. A time-out of the  
Watch-Dog Timer generates either an interrupt or a system reset. The WDT_RES Flash  
Option Bit determines the time-out response of the Watch-Dog Timer. Refer to the chapter  
“Flash Option Bits” on page 138 for information regarding programming of the WDT_RES  
Flash Option Bit.  
WDT Interrupt in Normal Operation  
If configured to generate an interrupt when a time-out occurs, the Watch-Dog Timer issues  
an interrupt request to the interrupt controller and sets the WDTstatus bit in the Watch-Dog  
Timer Control register. If interrupts are enabled, the eZ8 CPU responds to the interrupt  
request by fetching the Watch-Dog Timer interrupt vector and executing code from the  
vector address. After time-out and interrupt generation, the Watch-Dog Timer counter  
rolls over to its maximum value of FFFFFHand continues counting. The Watch-Dog  
Timer counter is not automatically returned to its Reload Value.  
The Reset Status Register (page 26) must be read before clearing the WDT interrupt. This  
read clears the WDT timeout flag and prevents further WDT interrupts for immediately  
occurring.  
PS024705-0405  
P R E L I M I N A R Y  
Watch-Dog Timer