欢迎访问ic37.com |
会员登录 免费注册
发布采购

Z8F082ASH020SC 参数 Datasheet PDF下载

Z8F082ASH020SC图片预览
型号: Z8F082ASH020SC
PDF下载: 下载PDF文件 查看货源
内容描述: Z8喝采XP -R F08xA系列与扩展外设 [Z8 Encore XP-R F08xA Series with eXtended Peripherals]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 244 页 / 2750 K
品牌: ZILOG [ ZILOG, INC. ]
 浏览型号Z8F082ASH020SC的Datasheet PDF文件第91页浏览型号Z8F082ASH020SC的Datasheet PDF文件第92页浏览型号Z8F082ASH020SC的Datasheet PDF文件第93页浏览型号Z8F082ASH020SC的Datasheet PDF文件第94页浏览型号Z8F082ASH020SC的Datasheet PDF文件第96页浏览型号Z8F082ASH020SC的Datasheet PDF文件第97页浏览型号Z8F082ASH020SC的Datasheet PDF文件第98页浏览型号Z8F082ASH020SC的Datasheet PDF文件第99页  
Z8 Encore! XP® F08xA Series  
Product Specification  
77  
number of cycles time delay before the Timer Output and the Timer Output  
Complement is forced to High (1).  
1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0)  
when the timer is disabled. When enabled, the Timer Output is forced Low (0) upon  
PWM count match and forced High (1) upon Reload.When enabled, the Timer Output  
Complement is forced High (1) upon PWM count match and forced Low (0) upon  
Reload. The PWMD field in TxCTL0 register is a programmable delay to control the  
number of cycles time delay before the Timer Output and the Timer Output  
Complement is forced to Low (0).  
CAPTURE RESTART mode  
0 = Count is captured on the rising edge of the Timer Input signal.  
1 = Count is captured on the falling edge of the Timer Input signal.  
COMPARATOR COUNTER mode  
When the timer is disabled, the Timer Output signal is set to the value of this bit.  
When the timer is enabled, the Timer Output signal is complemented upon timer  
Reload.  
When the Timer Output alternate function TxOUT on a GPIO port pin is enabled, Tx-  
OUT will change to whatever state the TPOL bit is in.The timer does not need to be en-  
abled for that to happen. Also, the Port data direction sub register is not needed to be set  
to output on TxOUT. Changing the TPOL bit with the timer enabled and running does  
not immediately change the TxOUT.  
Caution:  
PRES—Prescale value.  
The timer input clock is divided by 2PRES, where PRES can be set from 0 to 7. The pres-  
caler is reset each time the Timer is disabled. This reset ensures proper clock division each  
time the Timer is restarted.  
000 = Divide by 1  
001 = Divide by 2  
010 = Divide by 4  
011 = Divide by 8  
100 = Divide by 16  
101 = Divide by 32  
110 = Divide by 64  
111 = Divide by 128  
TMODE—Timer mode  
This field along with the TMODEHI bit in TxCTL0 register determines the operating  
mode of the timer. TMODEHI is the most significant bit of the Timer mode selection  
value.  
0000 = One-Shot mode  
0001 = Continuous mode  
0010 = Counter mode  
PS024705-0405  
P R E L I M I N A R Y  
Timers  
 复制成功!