Z8 Encore! XP® F08xA Series
Product Specification
82
All three Watch-Dog Timer Reload registers must be written in the order just listed. There
must be no other register writes between each of these operations. If a register write
occurs, the lock state machine resets and no further writes can occur unless the sequence is
restarted. The value in the Watch-Dog Timer Reload registers is loaded into the counter
when the Watch-Dog Timer is first enabled and every time a WDT instruction is executed.
Watch-Dog Timer Control Register Definitions
Watch-Dog Timer Control Register
The Watch-Dog Timer Control (WDTCTL) register is a write-only control register. Writ-
ing the 55H, AAHunlock sequence to the WDTCTL register address unlocks the three
Watch-Dog Timer Reload Byte registers (WDTU, WDTH, and WDTL) to allow changes
to the time-out period. These write operations to the WDTCTL register address produce
no effect on the bits in the WDTCTL register. The locking mechanism prevents spurious
writes to the Reload registers.
This register address is shared with the read-only Reset Status Register.
Table 56. Watch-Dog Timer Control Register (WDTCTL)
BITS
7
6
5
4
3
2
1
0
WDTUNLK
FIELD
RESET
R/W
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
FF0H
ADDR
WDTUNLK—Watch-Dog Timer Unlock
The user software must write the correct unlocking sequence to this register before it is
allowed to modify the contents of the watch-dog timer reload registers.
Watch-Dog Timer Reload Upper, High and Low Byte Registers
The Watch-Dog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) reg-
isters (Tables 57 through 59) form the 24-bit reload value that is loaded into the Watch-
Dog Timer when a WDT instruction executes. The 24-bit reload value is {WDTU[7:0],
WDTH[7:0], WDTL[7:0]}. Writing to these registers sets the appropriate Reload Value.
Reading from these registers returns the current Watch-Dog Timer count value.
PS024705-0405
P R E L I M I N A R Y
Watch-Dog Timer
ZILOG [ ZILOG, INC. ]
