Z8 Encore! XP® F08xA Series
Product Specification
205
Figure 36 and Table 131 provide timing information for UART pins for the case where
CTS is not used for flow control. DE asserts after the transmit data register has been writ-
ten. DE remains asserted for multiple characters as long as the transmit data register is
written with the next character before the current character has completed.
T2
DE
(Output)
TXD
(Output)
start
bit0
bit 1
bit 7 parity
stop
T1
end of
stop bit(s)
Figure 36. UART Timing Without CTS
Table 131. UART Timing Without CTS
Delay (ns)
Parameter
UART
Abbreviation
Minimum
Maximum
T
DE assertion to TXD falling edge (start bit) delay 1 * XIN
period
1 bit time
1
T
End of Stop Bit(s) to DE deassertion delay (Tx
data register is empty)
± 5
2
PS024705-0405
P R E L I M I N A R Y
Electrical Characteristics
ZILOG [ ZILOG, INC. ]
