Z8 Encore! XP® F08xA Series
Product Specification
204
UART Timing
Figure 35 and Table 130 provide timing information for UART pins for the case where
CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the transmit
data register has been loaded with data prior to CTS assertion.
CTS
(Input)
T3
DE
(Output)
T1
TXD
bit 7 parity
stop
start
bit 0
bit 1
(Output)
T2
end of
stop bit(s)
Figure 35. UART Timing With CTS
Table 130. UART Timing With CTS
Delay (ns)
Parameter
UART
Abbreviation
Minimum
Maximum
T
CTS Fall to DE output delay
2 * XIN
period
2 * XIN period
+ 1 bit time
1
T
T
DE assertion to TXD falling edge (start bit) delay ± 5
End of Stop Bit(s) to DE deassertion delay ± 5
2
3
PS024705-0405
P R E L I M I N A R Y
Electrical Characteristics
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