Z8 Encore! XP® F08xA Series
Product Specification
201
TCLK
System
Clock
Port Value
Changes to 0
Port Pin
Input Value
Port Input Data
Register Latch
0 Latched
Into Port Input
Data Register
Port Input Data Register
Value 0 Read
by eZ8
Port Input Data
Read on Data Bus
Figure 32. Port Input Sample Timing
Table 127. GPIO Port Input Timing
Delay (ns)
Parameter Abbreviation
Minimum Maximum
T
T
T
Port Input Transition to XIN Rise Setup Time
(Not pictured)
5
–
S_PORT
H_PORT
SMR
XIN Rise to Port Input Transition Hold Time
(Not pictured)
0
–
GPIO Port Pin Pulse Width to ensure STOP Mode
Recovery
1µs
(for GPIO Port Pins enabled as SMR sources)
PS024705-0405
P R E L I M I N A R Y
Electrical Characteristics
ZILOG [ ZILOG, INC. ]
