Z8 Encore! XP® F08xA Series
Product Specification
203
On-Chip Debugger Timing
Figure 34 and Table 129 provide timing information for the DBG pin. The DBG pin tim-
ing specifications assume a 4ns maximum rise and fall time.
TCLK
XIN
T1
T2
T4
DBG
(Output)
Output Data
T3
DBG
(Input)
Input Data
Figure 34. On-Chip Debugger Timing
Table 129. On-Chip Debugger Timing
Delay (ns)
Parameter
DBG
Abbreviation
Minimum
Maximum
T
T
T
T
XIN Rise to DBG Valid Delay
–
2
5
5
15
–
1
2
3
4
XIN Rise to DBG Output Hold Time
DBG to XIN Rise Input Setup Time
DBG to XIN Rise Input Hold Time
–
–
PS024705-0405
P R E L I M I N A R Y
Electrical Characteristics