Z8 Encore! XP® 4K Series
Product Specification
57
IRQ0 Enable High and Low Bit Registers
Table 37 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters (Tables 38 and 39) form a priority encoded enabling for interrupts in the Interrupt
Request 0 register.
Table 37. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Medium
High
where x indicates the register bits from 0–7.
Table 38. IRQ0 Enable High Bit Register (IRQ0ENH)
BITS
7
6
5
4
3
2
1
0
Reserved
T1ENH
T0ENH
U0RENH U0TENH Reserved Reserved ADCENH
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC1H
ADDR
Reserved—Must be 0.
T1ENH—Timer 1 Interrupt Request Enable High Bit
T0ENH—Timer 0 Interrupt Request Enable High Bit
U0RENH—UART 0 Receive Interrupt Request Enable High Bit
U0TENH—UART 0 Transmit Interrupt Request Enable High Bit
ADCENH—ADC Interrupt Request Enable High Bit
Table 39. IRQ0 Enable Low Bit Register (IRQ0ENL)
BITS
7
6
5
4
3
2
1
0
Reserved
T1ENL
T0ENL
U0RENL U0TENL Reserved Reserved ADCENL
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R
R
R/W
FC2H
ADDR
Reserved—Must be 0.
PS022815-0206
Interrupt Controller
ZILOG [ ZILOG, INC. ]
