Z8 Encore! XP® 4K Series
Product Specification
61
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
just by switching from one shared source to another. For this reason, an interrupt must be
disabled before switching between sources.
Table 47. Shared Interrupt Select Register (IRQSS)
BITS
7
6
5
4
3
2
1
0
PA7VS
PA6CS
Reserved
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FCEH
ADDR
PA7VS—PA7/LVD Selection
0 = PA7 is used for the interrupt for PA7VS interrupt request.
1 = The LVD is used for the interrupt for PA7VS interrupt request.
PA6CS—PA6/Comparator Selection
0 = PA6 is used for the interrupt for PA6CS interrupt request.
1 = The Comparator is used for the interrupt for PA6CS interrupt request.
Reserved—Must be 0.
Interrupt Control Register
The Interrupt Control (IRQCTL) register (Table 48) contains the master enable bit for all
interrupts.
Table 48. Interrupt Control Register (IRQCTL)
BITS
7
6
5
4
3
2
1
0
IRQE
Reserved
FIELD
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
FCFH
ADDR
IRQE—Interrupt Request Enable
This bit is set to 1 by executing an EI (Enable Interrupts) or IRET (Interrupt Return)
instruction, or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI
instruction, eZ8 CPU acknowledgement of an interrupt request, Reset or by a direct regis-
ter write of a 0 to this bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
Reserved—Must be 0.
PS022815-0206
Interrupt Controller
ZILOG [ ZILOG, INC. ]
