Z8 Encore! XP® 4K Series
Product Specification
173
commands are disabled. Table 109 on page 177 is a summary of the On-chip debugger
commands. Each OCD command is described in further detail in the bulleted list follow-
ing this table. Table 109 also indicates those commands that operate when the device is not
in DEBUG mode (normal operation) and those commands that are disabled by program-
ming the Flash Read Protect Option bit.
Command Enabled when NOT
Disabled by
Debug Command
Byte
00H
01H
02H
03H
04H
05H
06H
07H
08H
in DEBUG mode?
Flash Read Protect Option Bit
Read OCD Revision
Reserved
Yes
–
–
–
Read OCD Status Register
Read Runtime Counter
Write OCD Control Register
Read OCD Control Register
Write Program Counter
Read Program Counter
Write Register
Yes
–
–
–
Yes
Yes
–
Cannot clear DBGMODE bit
–
Disabled
Disabled
–
–
Only writes of the Flash Memory Control
registers are allowed. Additionally, only
the Mass Erase command is allowed to
be written to the Flash Control register.
Read Register
09H
0AH
–
–
–
–
–
–
–
–
–
–
–
Disabled
Disabled
Disabled
Yes
Write Program Memory
Read Program Memory
Write Data Memory
Read Data Memory
Read Program Memory CRC
Reserved
0BH
0CH
0DH
–
0EH
–
0FH
–
Step Instruction
10H
Disabled
Disabled
Disabled
–
Stuff Instruction
11H
Execute Instruction
Reserved
12H
13H–FFH
In the following bulleted list of OCD Commands, data and commands sent from the host
to the On-Chip Debugger are identified by ’DBG← Command/Data’. Data sent from the
On-Chip Debugger back to the host is identified by ’DBG→ Data’
PS022815-0206
On-Chip Debugger
ZILOG [ ZILOG, INC. ]
