Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
R253 RP
R250 IRQ
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register File
Working Register Pointer
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = P30 Input
IRQ4 = T0
Default After Reset = 00H
IRQ5 = T1
Inter Edge
P31 ↓ P32 ↓ = 00
P31 ↓ P32 ↑ = 01
P31 ↑ P32 ↓ = 10
P31 ↑↓ P32 ↑↓ = 11
Figure 58. Register Pointer
FDH: Read/Write
Default After Reset = 00H
R254 SPH
D7 D6 D5 D4 D3 D2 D1 D0
Figure 55. Interrupt Request Register
FAH: Read/Write
(Z86E40)
Stack Pointer Upper
Byte (SP8 - SP15)
R251 IMR
(Z86E30/E31)
0 = 0 State
D7 D6 D5 D4 D3 D2 D1 D0
1 = 1 State
1
Enables IRQ5-IRQ0
(D0 = IRQ0)
Figure 59. Stack Pointer High
FEH: Read/Write
1 Enables RAM Protect †
Enables Interrupts
1
† This option must be selected when ROM code is
submitted for ROM Masking, otherwise this control bit
is disabled permanently.
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
Figure 56. Interrupt Mask Register
FBH: Read/Write
Stack Pointer Lower
Byte (SP0 - SP7)
R252 FLAGS
D7 D6 D5 D4 D3 D2 D1 D0
Figure 60. Stack Pointer Low
FFH: Read/Write
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 57. Flag Register
FCH: Read/Write
60
P R E L I M I N A R Y
DS97Z8X0500
ZILOG [ ZILOG, INC. ]
