Z86E30/E31/E40
Z8 4K OTP Microcontroller
Zilog
EXPANDED REGISTER FILE CONTROL REGISTERS
PCON (FH) 00H
WDTMR (F) 0F
1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC System Clock
Comparator Output Port 3
0 P34, P37 Standard*
1 P34, P37 Comparator Output
00
01
10
11
5 ms
10 ms
20 ms
80 ms
128 SCLK
256 SCLK
512 SCLK
2048 SCLK
*
0
1
Port 1 Open-Drain
Port 1 Push-PullActive*†
WDT During HALT
0
1
OFF
ON *
0
1
Port 0 Open-Drain
Port 0 Push-pullActive*
WDT During STOP
0
1
Port 0 Low EMI
Port 0 Standard*
0
1
OFF
ON
*
0
1
Port 1 Low EMI
Port 1 Standard*†
XTAL1/INT RC Select for WDT
0
1
On-Board RC
XTAL
*
0
1
Port 2 Low EMI
Port 2 Standard*
Reserved (Must be 0)
0
1
Port 3 Low EMI
Port 3 Standard*
* Default setting after RESET
Low EMI Oscillator
0
1
Low EMI
Standard*
* Default SettingAfter Reset
† Must Be 1 for Z86E30/E31
Figure 43. Watch-Dog Timer Mode Register
Write Only
Figure 41. Port Configuration Register
Write Only
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
SMR (FH) 0B
D7 D6 D5 D4 D3 D2 D1 D0
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
SCLK/TCLK Divide-by-16
0
1
OFF
ON
**
Reserved (Must be 0)
Note: Not used in conjunction with SMR Source
External Clock Divide by 2
0
1
SCLK/TCLK =XTAL/2*
SCLK/TCLK =XTAL
Stop Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
Figure 44. STOP-Mode Recovery Register 2
Write Only
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0
1
OFF
ON*
Stop Recovery Level
0
1
Low*
High
Stop Flag
0
1
POR*
Stop Recovery
* Default setting after RESET.
** Default setting after RESET and STOP-Mode Recovery.
Figure 42. STOP-Mode Recovery Register
Write Only Except Bit D7, Which is Read Only
DS97Z8X0500
P R E L I M I N A R Y
57
ZILOG [ ZILOG, INC. ]
